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Kavita Nair, Ph.D.


Department of Engineering, Aviation and Technology
Electrical and Computer Engineering


Education

Ph.D., Electrical and Computer Engineering University of Minnesota, US
M.S., Electrical and Computer Engineering University of Minnesota, US

Practice Areas

Analog: Mixed-signal design, Switched capacitor and Low power circuit design, Data converters, Microwave & RF circuits, bandgap, temp/process sensors, PLL, etc.
Digital: SRAM/eDRAM design, Power Analysis of Digital Circuits, Layout automation for digital logic blocks, Cadence Virtuoso, Spectre and SPICE simulation, VHDL and Verilog verification, Ultrasim & Power Analysis.

Publications and Media Placements

"A 45 nm SOI Embedded DRAM Macro for the POWERTM Processor 32 MByte On-Chip L3 Cache", John Barth, Donald Plass, Eric Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, Toshi Kirihata, William Reohr, Kavita Nair and Nianzheng Cao, IEEE Journal of Solid-State Circuits, Volume: 46 , Issue: 1, pp. 64-75, 2011.

"A 45nm SOI Embedded DRAM Macro for POWER7TM 32MB On-Chip L3 Cache"
, John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, William Reohr, Kavita Nair and Nianzheng Cao, ISSCC 2010 Digest of Technical Papers, pp. 342- 343.

"POWER7 (TM) Microprocessor Design - SRAM arrays"
, IBM Journal of Research and Development, Volume. 51, No. 6, November 2007

Kavita Nair and Ramesh Harjani, "Correction for pipelined analog to digital (A/D) converter", Publication number US6784814 B1, Publication date Aug 31, 2004.

"A 96dB SFDR 50MS/s Digital Enhanced Pipeline Data Converter"
, Kavita Nair and Ramesh Harjani, Proc. of International Solid State Circuits Conference 2004.

"High speed, high SFDR data converter design"
, Kavita Nair and Ramesh Harjani, Semiconductor Research Corporation, Paper Publication ID P006516, August 2003.

"Data acquisition and Conversion"
, Kavita Nair, Chris Z, Dennis Polla and Ramesh Harjani, Chapter in ‘Wiley Encyclopedia of Electrical and Electronics Engineering' edited By John Webster, 1999.

"Compact ultra-low power, programmable continuous-time filter banks for feedback cancellation in hearing aids"
, Kavita Nair and Ramesh Harjani, Proc. of the IEEE 12th International Conference on VLSI Design, pp. 55-60, Jan 1999.

"A telemetry and interface circuits for piezoelectric sensors", Kavita Nair and Ramesh Harjani, Proc. of the IEEE International Symposium on Circuits and Systems, pp. 152-155, vol. 5, 1999.

"An ultra-low power transconductance cell"
, Kavita Nair and Ramesh Harjani, Proc. of the IEEE International Symposium on Circuits and Systems, pp. 217-220, 1996.

Honors and Awards

  • 2010 Lewis Winner Award for Outstanding Paper: "A 45nm SOI Embedded DRAM Macro for POWER7 32MB On-Chip L3 Cache".
  • IBM Engineer Recognition Award 2005.
  • Inventor Recognition Award, TECHON 2004.
  • Semiconductor Research Corporation/Texas Instruments Graduate Fellowship (1999-2003).
  • Numerous technical publications, Chapter in Encyclopedia of Electrical Eng. and Patent.