Jorge Martínez, Ph.D.
Department of Mathematics and Computer Science
Ph.D. Computer Science, Universidad Antonio de Nebrija, Madrid (Spain)
M.S. Computer Science, Universidad Complutense de Madrid (Spain)
- Fault tolerance and reliability
Publications and Media Placements
Reviriego, J. Martínez, O. Rottenstreich, S. Liu, F. Lombardi. Remove Minimum (RM):
An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog. Transactions on
Dependable and Secure Computing, (ISSN: 1545-5971), Vol. 19, No. 2, pp. 966 – 977,
Reviriego, J. Martínez, M. Ottavi. Soft Error Tolerant Count Min Sketches. IEEE Transactions on Computers, (ISSN: 0018-9340), Vol. 70, No. 2, pp. 284-290, February 2021.
Reviriego, J. Martínez, S. Pontarelli. Cuckoo Filters and Bloom Filters: Comparison and Application to Packet Classification. IEEE Transactions on Network and Service Management, (ISSN: 1932-4537), Vol. 17, No. 14, pp. 2690 - 2701, September 2020.
Reviriego, J. Martínez, S. Pontarelli. Improving Packet Flow Counting with Fingerprint Counting. IEEE Communications Letters, (ISSN: 1089-7798), Vol. 24, No. 1, pp. 76-80, January 2020.
Reviriego, J. Martínez, S. Pontarelli. CFBF: Reducing the Insertion Time of Cuckoo Filters with an Integrated Bloom Filter. IEEE Communications Letters, (ISSN: 1089-7798), Vol. 23, No. 10, pp. 1857-1861, October 2019.
Martínez, P. Reviriego, S. Pontarelli. Accelerating Packet Classification with Two Class Cuckoo Filters (TC-CF). Sixth International Conference on Software Defined Systems (SDS 2019), Rome (Italy). June 10-13, 2019.
Martinez, M. Atamaner, P. Reviriego, O. Ergin, M. Ottavi, Opcode Vector: An Efficient Scheme to Detect Soft Errors in Instructions, Microelectronics Reliability, Vol. 86, pp. 92-97, July 2018.
Martinez, J.A. Maestro, P. Reviriego, Evaluating the Impact of the Instruction Set on Microprocessor Reliability to Soft Errors, IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 18, No. 1, March 2018.
Martínez, J.A. Maestro, P. Reviriego, A Generalized Scheme to Enhance Error Detection in the Instruction Set Architecture, Design of Circuits and Integrated Systems Conference (DCIS 2017), Barcelona (Spain), November 22-24, 2017.
Martínez, J.A. Maestro, P. Reviriego, A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture, IEEE Computer Architecture Letters (ISSN: 1556-6056), Vol. 16, No. 2, pp. 103-106, July-December 2017.
P. Reviriego, J. Martínez, S. Pontarelli, J.A. Maestro, A Method to Design SEC-DED-DAEC codes with Optimized Decoding, IEEE Transactions on Device and Materials Reliability (ISSN: 1530-4388), Vol. 14, No. 3, pp. 884-889, September 2014.